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| author | 4pplet <mail@4pplet.com> | 2022-05-12 00:37:43 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-11 16:37:43 -0700 |
| commit | ddba52325cee971c83aeb030536340f79db37204 (patch) | |
| tree | 4d2b81aff2ac6e5972103dea54b2f7e375573f41 /keyboards/4pplet/yakiimo/rev_a/mcuconf.h | |
| parent | df9c266f45c947a2ae71f213096ef0d832f3e336 (diff) | |
| download | qmk_firmware-ddba52325cee971c83aeb030536340f79db37204.tar.gz qmk_firmware-ddba52325cee971c83aeb030536340f79db37204.zip | |
[Keyboard] Yakiimo PCB (#16984)
Co-authored-by: Joel Challis <git@zvecr.com>
Co-authored-by: Ryan <fauxpark@gmail.com>
Co-authored-by: 4pplet <4pplet@protonmail.com>
Co-authored-by: 4pplet <stefan.ess@gmail.com>
Diffstat (limited to 'keyboards/4pplet/yakiimo/rev_a/mcuconf.h')
| -rw-r--r-- | keyboards/4pplet/yakiimo/rev_a/mcuconf.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/keyboards/4pplet/yakiimo/rev_a/mcuconf.h b/keyboards/4pplet/yakiimo/rev_a/mcuconf.h new file mode 100644 index 0000000000..566a38124d --- /dev/null +++ b/keyboards/4pplet/yakiimo/rev_a/mcuconf.h @@ -0,0 +1,37 @@ +/* Copyright 2020 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * This file was auto-generated by: + * `qmk chibios-confmigrate -i keyboards/acheron/austin/mcuconf.h -r platforms/chibios/GENERIC_STM32_F072XB/configs/mcuconf.h` + */ + +#pragma once + +#include_next <mcuconf.h> +#undef STM32_PLLM_VALUE +#undef STM32_PLLN_VALUE +#undef STM32_PLLP_VALUE +#undef STM32_PLLQ_VALUE +#undef STM32_PPRE1 +#undef STM32_PPRE2 + +#define STM32_PLLM_VALUE 4 +#define STM32_PLLN_VALUE 168 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 7 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV1 |