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| author | Drashna Jael're <drashna@live.com> | 2022-01-30 13:23:13 -0800 |
|---|---|---|
| committer | Drashna Jael're <drashna@live.com> | 2022-01-30 13:23:13 -0800 |
| commit | b57f8a8b9fd50bdb39473e7730400e14b879da72 (patch) | |
| tree | 430a140a24cf571b87423bdcd1fa5ad0a0461364 /keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h | |
| parent | 1be1bebc043483c5a8fc77ed8b2705676a6cb05c (diff) | |
| parent | 941b1d35b8e40a9c93301a1131ef3f3336fee0b5 (diff) | |
| download | qmk_firmware-b57f8a8b9fd50bdb39473e7730400e14b879da72.tar.gz qmk_firmware-b57f8a8b9fd50bdb39473e7730400e14b879da72.zip | |
Merge remote-tracking branch 'origin/master' into develop
Diffstat (limited to 'keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h')
| -rw-r--r-- | keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h b/keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h new file mode 100644 index 0000000000..d868eae48e --- /dev/null +++ b/keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h @@ -0,0 +1,55 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <https://www.gnu.org/licenses/>. + */ + +#pragma once + +#include_next "mcuconf.h" + +#undef STM32_I2C_USE_I2C1 +#define STM32_I2C_USE_I2C1 TRUE + +#undef STM32_I2C_I2C1_RX_DMA_STREAM +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#undef STM32_I2C_I2C1_TX_DMA_STREAM +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +#undef STM32_PWM_USE_TIM2 +#define STM32_PWM_USE_TIM2 TRUE + +#undef STM32_PWM_USE_TIM3 +#define STM32_PWM_USE_TIM3 TRUE + +#undef STM32_SPI_USE_SPI1 +#define STM32_SPI_USE_SPI1 TRUE + +#undef STM32_SPI_SPI1_RX_DMA_STREAM +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#undef STM32_SPI_SPI1_TX_DMA_STREAM +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +#undef STM32_SERIAL_USE_USART2 +#define STM32_SERIAL_USE_USART2 TRUE + +#undef STM32_UART_USART2_RX_DMA_STREAM +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#undef STM32_UART_USART2_TX_DMA_STREAM +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +#undef STM32_GPT_USE_TIM4 +#define STM32_GPT_USE_TIM4 TRUE + +#undef STM32_ST_USE_TIMER +#define STM32_ST_USE_TIMER 5 |