ibm4704_usb: Fix interrupt of clock(rising edge)

1 files changed, 18 insertions, 21 deletions

diff --git a/tmk_core/protocol/ibm4704.c b/tmk_core/protocol/ibm4704.c
index a10a5e74d9..a2c6700477 100644
--- a/tmk_core/protocol/ibm4704.c
+++ b/tmk_core/protocol/ibm4704.c
@@ -104,50 +104,47 @@ uint8_t ibm4704_recv_response(void)
     return rbuf_dequeue();
 }
 
+uint8_t ibm4704_recv(void)
+{
+    if (rbuf_has_data()) {
+        return rbuf_dequeue();
+    } else {
+        return -1;
+    }
+}
+
 /*
 Keyboard to Host
 ----------------
 Data bits are LSB first and Parity is odd. Clock has around 60us high and 30us low part.
 
-        ____      __   __   __   __   __   __   __   __   __   ________
-Clock       \____/  \_/  \_/  \_/  \_/  \_/  \_/  \_/  \_/  \_/
+        ____       __   __   __   __   __   __   __   __   __   _______
+Clock       \_____/  \_/  \_/  \_/  \_/  \_/  \_/  \_/  \_/  \_/
              ____ ____ ____ ____ ____ ____ ____ ____ ____ ____    
 Data    ____/    X____X____X____X____X____X____X____X____X____X________
             Start   0    1    2    3    4    5    6    7    P  Stop
 
 Start bit:  can be long as 300-350us.
 Inhibit:    Pull Data line down to inhibit keyboard to send.
-Timing:     Host reads bit while Clock is hi.
+Timing:     Host reads bit while Clock is hi.(rising edge)
 Stop bit:   Keyboard pulls down Data line to lo after 9th clock.
 */
-uint8_t ibm4704_recv(void)
-{
-    if (rbuf_has_data()) {
-        return rbuf_dequeue();
-    } else {
-        return -1;
-    }
-}
-
 ISR(IBM4704_INT_VECT)
 {
     static enum {
-        INIT, START, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PARITY,
-    } state = INIT;
+        STOP, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PARITY
+    } state = STOP;
     // LSB first
     static uint8_t data = 0;
     // Odd parity
     static uint8_t parity = false;
 
     ibm4704_error = 0;
-    // return unless falling edge
-    if (clock_in()) { goto RETURN; }    // why this occurs?
 
-    state++;
-    switch (state) {
-        case START:
+    switch (state++) {
+        case STOP:
             // Data:Low
-            WAIT(data_hi, 10, state);
+            WAIT(data_lo, 10, state);
             break;
         case BIT0:
         case BIT1:
@@ -182,7 +179,7 @@ ERROR:
     while (ibm4704_send(0xFE)) _delay_ms(1); // resend
     xprintf("R:%02X%02X\n", state, data);
 DONE:
-    state = INIT;
+    state = STOP;
     data = 0;
     parity = false;
 RETURN: